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philips semiconductors pca9531 8-bit i 2 c led dimmer product data 2003 nov 10 integrated circuits
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2 2003 nov 10 features ? eight led drivers (on, off, flashing at a programmable rate) ? two selectable, fully programmable blink rates (frequency and duty cycle) between 0.625 and 160 hz (1.6 and 6.25 milliseconds) ? 256 brightness steps ? input/outputs not used as led drivers can be used as regular gpios ? internal oscillator requires no external components ? i 2 c interface logic compatible with smbus ? internal power-on reset ? noise filter on scl/sda inputs ? active low reset input ? eight open drain outputs directly drive leds to 25 ma ? edge rate control on outputs ? no glitch on power-up ? supports hot insertion ? low stand-by current ? operating power supply voltage range of 2.3 v to 5.5 v ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 150 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offer: so16, tssop16, hvqfn16 description the pca9531 is an 8-bit i 2 c & smbus i/o expander optimized for dimming leds in 256 discrete steps for red/green/blue (rgb) color mixing and back light applications. the pca9531 contains an internal oscillator with two user programmable blink rates and duty cycles coupled to the output pwm. the led brightness is controlled by setting the blink rate high enough (> 100 hz) that the blinking can not be seen and then using the duty cycle to vary the amount of time the led is on and thus the average current through the led. the initial setup sequence programs the two blink rates/duty cycles for each individual pwm. from then on, only one command from the bus master is required to turn individual leds on, off, blink rate 1 or blink rate 2. based on the programmed frequency and duty cycle, blink rate 1 and blink rate 2 will cause the leds to appear at a different brightness or blink at periods up to 1.6 second. the open drain outputs directly drive the leds with maximum output sink current of 25 ma per bit and 100 ma per package. to blink leds at periods greater than 1.6 second the bus master (mcu, mpu, dsp, chipset, etc.) must send repeated commands to turn the led on and off as is currently done when using normal i/o expanders like the philips pcf8574 or pca9554. any bits not used for controlling the leds can be used for general purpose parallel input/output (gpio) expansion which provides a simple solution when additional i/o is needed for acpi power switches, sensors, push-buttons, alarm monitoring, fans, etc. the active low hardware reset pin (reset) and power on reset (por) initializes the registers to their default state causing the bits to be set high (led off). three hardware address pins on the pca9531 allow eight devices to operate on the same bus. ordering information packages temperature range order code topside mark drawing number 16-pin plastic so -40 to +85 c pca9531d pca9531d sot109-1 16-pin plastic tssop -40 to +85 c pca9531pw pca9531 sot403-1 16-pin plastic hvqfn -40 to +85 c pca9531bs 9531 sot629-1 standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. i 2 c is a trademark of philips semiconductors corporation.
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 3 pin configuration ? so, tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sw02039 a0 a1 a2 led0 led1 led2 led3 v ss v dd sda scl reset led7 led6 led5 led4 figure 1. pin configuration ? so, tssop pin configuration ? hvqfn 12 11 10 9 5 6 7 8 1 2 3 4 16 15 14 13 su01667 top view a2 led0 led1 led2 led3 led4 v ss led5 reset led6 led7 sda v dd a0 a1 scl figure 2. pin configuration ? hvqfn pin description so, tssop pin number hvqfn pin number symbol function 1 15 a0 address input 0 2 16 a1 address input 1 3 1 a2 address input 2 4, 5, 6, 7 2, 3, 4, 5 led0-3 led drivers 0-3 8 6 v ss supply ground 9, 10, 11, 12 7, 8, 9, 10 led4-7 led drivers 4-7 13 11 reset active low reset input 14 12 scl serial clock line 15 13 sda serial data line 16 14 v dd supply voltage
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 4 block diagram pwm0 register pwm1 register prescaler 0 register prescaler 1 register i 2 c-bus control ledx a1 input filters scl sda oscillator power-on reset v dd v ss sw02040 1 0 blink0 blink1 reset note: only one i/o shown for clarity led select (lsx) register input register pca9531 a2 a0 figure 3. block diagram
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 5 device addressing following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9531 is shown in figure 4. to conserve power, no internal pullup resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. 1 1 0 0 a2 a1 a0 slave address su01420 fixed hardware selectable r/w figure 4. slave address the last bit of the address byte defines the operation to be performed. when set to logic 1 a read is selected while a logic 0 selects a write operation. control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9531 which will be stored in the control register. 0 0 ai b2 b1 b0 0 sw01034 0 auto-increment flag register address reset state: 00h figure 5. control register control register definition b2 b1 b0 register name type register function 0 0 0 input read input register 0 0 1 psc0 read/ write frequency prescaler 0 0 1 0 pwm0 read/ write pwm register 0 0 1 1 psc1 read/ write frequency prescaler 1 1 0 0 pwm1 read/ write pwm register 1 1 0 1 ls0 read/ write led0-led3 selector 1 1 0 ls1 read/ write led4-led7 selector register description the lowest 3 bits are used as a pointer to determine which register will be accessed. if the auto-increment flag is set, the three low order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. the contents of these bits will rollover to ?000? after the last register is accessed. when auto-increment flag is set (ai = 1) and a read sequence is initiated, the sequence must start by reading a register different from the input register (b2 b1 b0 0 0 0). only the 3 least significant bits are affected by the ai flag. unused bits must be programmed with zeroes. input ? input register bit 7 6 5 4 3 2 1 0 default x x x x x x x x the input register reflects the state of the device pins. writes to this register will be acknowledged but will have no effect. psc0 ? frequency prescaler 0 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 psc0 is used to program the period of the pwm output. the period of blink0 (psc0 1) 152 pwm0 ? pwm register 0 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 the pwm0 register determines the duty cycle of blink0. the outputs are low (led on) when the count is less than the value in pwm0 and high (led off) when it is greater. if pwm0 is programmed with 00h, then the pwm0 output is always high (led off). the duty cycle of blink0 is: pwm0 256 psc1 ? frequency prescaler 1 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 psc1 is used to program the period of pwm output. the period of blink1 (psc1 1) 152 pwm1 ? pwm register 1 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 the pwm1 register determines the duty cycle of blink1. the outputs are low (led on) when the count is less than the value in pwm1 and high (led off) when it is greater. if pwm1 is programmed with 00h, then the pwm1 output is always high (led off) . the duty cycle of blink1 is: pwm1 256 ls0 ? led0-3 selector led 3 led 2 led 1 led 0 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 ls1 ? led4-7 selector led 7 led 6 led 5 led 4 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 the lsx led select registers determine the source of the led data. 00 = output is set hi-z (led off - default) 01 = output is set low (led on) 10 = output blinks at pwm0 rate 11 = output blinks at pwm1 rate
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 6 power-on reset when power is applied to v dd , an internal power on reset holds the pca9531 in a reset state until v dd has reached v por . at this point, the reset condition is released and the pca9531 registers are initialized to their default states, all the outputs in the off state. external reset a reset can be accomplished by holding the reset pin low for a minimum of t w . the pca9531 registers and i 2 c state machine will be held in their default state until the reset input is once again high. this input requires a pull-up resistor to v dd . characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 6). sda scl sw00363 data line stable; data valid change of data allowed figure 6. bit transfer start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 7). system configuration a device generating a message is a transmitter: a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 8). sda scl sw00365 s p sda scl start condition stop condition figure 7. definition of start and stop conditions master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl sw00366 i 2 c multiplexer slave figure 8. system configuration
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 7 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. eac h byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master ge nerates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges h as to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge r elated clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter scl from master sw00368 data output by receiver 12 89 s start condition clock pulse for acknowledgement acknowledge not acknowledge figure 9. acknowledgement on the i 2 c-bus
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 8 bus transactions 0 a1 a0 12 scl write to register data out from port 345678 sda s0a a a 1100a2 data 1 slave address data to register start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave t pv data 1 valid sw01081 9 b0 0 0 ai 0 b2 b1 command byte figure 10. write to register 0 0ai 0 a0 a2 0 0 a2 a1 a0 1 1 0 0 a0 1 1 s0 a a acknowledge from slave r/w acknowledge from slave a p na acknowledge from slave acknowledge from master s data data r/w first byte at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter last byte sw01082 no acknowledge from master 1 slave address data from register data from register slave address auto-increment register address if ai = 1 a1 b2 b1 b0 figure 11. read from register 110 0a2a1a0 read from port data into port sda s1a a data 1 data 4 slave address data from port data from port start condition r/w acknowledge from slave acknowledge from master stop condition t ps data 4 data 2 p data 3 t ph sw01084 no acknowledge from master na data 1 notes: 1. this figure assumes the command byte has previously been programmed with 00h. figure 12. read input port register
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 9 application data pca9531 a1 a0 v ss sda scl reset v dd i 2 c/smbus master sw02041 sda scl a2 led0 led1 led2 led3 led4 led5 led6 led7 5 v 5 v note: led0 to led5 are used as led drivers led6 and led7 are used as regular gpios. gpio figure 13. typical application minimizing i dd when the i/o is used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 13. since the led acts as a diode, when the led is off the i/o v in is about 1.2 v less than v dd . the supply current , i dd , increases as v in becomes lower than v dd and is specified as ? i dd in the dc characteristics table. designs needing to minimize current consumption, such as battery power applications, should consider maintaining the i/o pins g reater than or equal to v dd when the led is off. figure 14 shows a high value resistor in parallel with the led. figure 15 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v in at or above v dd and prevents additional supply current consumption when the led is off. v dd v dd ledx led 100 k sw02086 figure 14. high value resistor in parallel with the led v dd 3.3 v ledx led sw02087 5 v figure 15. device supplied by a lower voltage
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 10 programming example the following example will show how to set led0 to led3 on. it will then set led4 and led5 to blink at 1 hz at a 50% duty cycle. led6 and led7 will be set to be dimmed at 25% of their maximum brightness (duty cycle = 25%). table 1. i 2 c-bus start s pca9531 address with a0-a2 = low c0h psc0 subaddress + auto-increment 11h set prescaler psc0 to achieve a period of 1 second: blink period 1 psc0 1 152 psc0 = 151 97h set pwm0 duty cycle to 50%: pwm0 256 0.5 pwm0 = 128 80h set prescaler pcs1 to dim at max frequency: blink period max psc1 = 0 00h set pwm1 output duty cycle to 25%: pwm1 256 0.25 pwm1 = 64 40h set led0 to led3 on 55h set led4 and 5 to pwm0, and led6 or 7 to pwm1 fah stop p
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 11 absolute maximum ratings in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min max unit v dd supply voltage -0.5 6.0 v v i/o dc voltage on an i/o v ss - 0.5 5.5 v i i/o dc output current on an i/o ? +25 ma i ss supply current ? 200 ma p tot total power dissipation ? 400 mw t stg storage temperature range -65 +150 c t amb operating ambient temperature -40 +85 c handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirab le to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under ? handling mos devices ? . dc characteristics v dd = 2.3 to 5.5 v; v ss = 0 v; t amb = -40 to +85 c; unless otherwise specified. typ at 3.3 v and 25 c. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 ? 5.5 v i dd supply current operating mode; v dd = 5.5 v; v i = v dd or v ss ; f scl = 100 khz ? 350 500 a i stb standby current standby mode; v dd = 5.5 v; v i = v dd or v ss ; f scl = 0 khz ? 1.9 3.0 a ? i dd additional standby current standby mode; v dd = 5.5 v; every led i/o at v in = 4.3 v; f scl = 0 khz ? ? 800 a v por power-on reset voltage no load; v i = v dd or v ss ? 1.7 2.2 v input scl; input/output sda v il low level input voltage -0.5 ? 0.3 v dd v v ih high level input voltage 0.7 v dd ? 5.5 v i ol low level output current v ol = 0.4v 3 6.5 ? ma i l leakage current v i = v dd = v ss -1 ? +1 a c i input capacitance v i = v ss ? 3.7 5 pf i/os v il low level input voltage -0.5 ? 0.8 v v ih high level input voltage 2.0 ? 5.5 v v ol = 0.4 v; v dd = 2.3 v; note 1 9 ? ? ma v ol = 0.4 v; v dd = 3.0 v; note 1 12 ? ? ma v ol = 0.4 v; v dd = 5.0 v; note 1 15 ? ? ma i ol low level output current v ol = 0.7 v; v dd = 2.3 v; note 1 15 ? ? ma v ol = 0.7 v; v dd = 3.0 v; note 1 20 ? ? ma v ol = 0.7 v; v dd = 5.0 v; note 1 25 ? ? ma i l input leakage current v dd = 3.6 v; v i = 0 or v dd -1 ? 1 a c io input/output capacitance ? 2.5 5 pf select inputs a0, a1, a2 / reset v il low level input voltage -0.5 ? 0.8 v v ih high level input voltage; a0 / reset 2.0 ? 5.5 v v ih high level input voltage; a1 / a2 2.0 ? v dd + 0.5 v i li input leakage current -1 ? 1 a c i input capacitance v i = v ss ? 2.3 5 pf note: 1. each i/o must be externally limited to a maximum of 25 ma and the device must be limited to a maximum current of 100 ma.
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 12 ac specifications symbol parameter standard mode i 2 c bus fast mode i 2 c bus units symbol parameter min max min max units f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 ? 1.3 ? s t hd;sta hold time after (repeated) start condition 4.0 ? 0.6 ? s t su;sta repeated start condition setup time 4.7 ? 0.6 ? s t su;sto setup time for stop condition 4.0 ? 0.6 ? s t hd;dat data in hold time 0 ? 0 ? ns t vd;ack valid time for ack condition 2 ? 600 ? 600 ns t vd;dat (l) data out valid time 3 ? 600 ? 600 ns t vd;dat (h) data out valid time 3 ? 1500 ? 600 ns t su;dat data setup time 250 ? 100 ? ns t low clock low period 4.7 ? 1.3 ? s t high clock high period 4.0 ? 0.6 ? s t f clock/data fall time ? 300 20 + 0.1 c b 1 300 ns t r clock/data rise time ? 1000 20 + 0.1 c b 1 300 ns t sp pulse width of spikes that must be suppressed by the input filters ? 50 ? 50 ns port timing t pv output data valid ? 200 ? 200 ns t ps input data setup time 100 ? 100 ? ns t ph input data hold time 1 ? 1 ? s reset t w reset pulse width 6 ? 6 ? ns t rec reset recovery time 0 ? 0 ? ns t reset 4,5 time to reset 400 ? 400 ? ns notes: 1. c b = total capacitance of one bus line in pf. 2. t vd;ack = time for acknowledgement signal from scl low to sda (out) low. 3. t vd;dat = minimum time for sda data out to be valid following scl low. 4. resetting the device while actively communicating on the bus may cause glitches or errant stop conditions. 5. upon reset, the full delay will be the sum of t reset and the rc time constant of the sda bus.
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 13 +10% 0% -10% -20% -30% -40% percent variation temperature ( c) -40 +20% 0 +25 +70 +85 max avg min sw01085 figure 16. typical frequency variation over process at v dd = 2.3 v to 3.0 v +10% 0% -10% -20% -30% -40% percent variation temperature ( c) -40 +20% 0 +25 +70 +85 max avg min sw01086 figure 17. typical frequency variation over process at v dd = 3.0 v to 5.5 v
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 14 sda scl sw01087 t rec t rec 50% 30% 50% 50% 50% t rec t w reset ledx led off ack or read cycle start figure 18. definition of reset timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 19. definition of timing
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 15 handbook, full pagewidth protocol scl sda t hd;sta t su;dat t hd;dat t vd;dat t f r t t buf t su;sta t low t high 1 / f scl start condition (s) bit 7 msb (a7) bit 6 (a6) t vd;ack sw02143 bit 8 (r/w ) acknowledge (a) stop condition (s) t su;sto figure 20. i 2 c-bus timing diagram; rise and fall times refer to v il and v ih pulse generator v i v o c l 50pf v dd definitions r l = load resistor. c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generators. v dd r t open d.u.t. r l = 500 ? sw02142 figure 21. test circuitry for switching times
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 16 so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 17 tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 18 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm sot629-1
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 19 revision history rev date description _1 20031110 product data (9397 750 12292); ecn 853-2407 30411 dated 06 september 2003. initial version
philips semiconductors product data pca9531 8-bit i 2 c led dimmer 2003 nov 10 20 purchase of philips i 2 c components conveys a license under the philips ? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 11-03 document order number: 9397 750 12292 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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